Field of the Invention
The invention relates to an integrated memory having memory cells and reference cells, and to an operating method for such a memory.
Memory devices of this type are described for example in U.S. Pat. Nos. 5,572,459 and 5,844,832. The memory devices described therein are of the FRAM (ferroelectric random access memory) type. These are ferroelectric memories, which are constructed similarly to DRAMs (Dynamic Random Access Memory) but whose storage capacitor has a ferroelectric dielectric. A differential sense amplifier is assigned to a respective bit line pair. A read access is effected simultaneously to a respective memory cell of two bit line pairs. A reference potential is generated on the respective other bit line of each bit line pair, the reference potential lying between two supply potentials of the memory. Each sense amplifier amplifies the differential signal present at its terminals, and thus the data read from the memory cells.
The reference potential is generated in the following way: firstly, the content of a reference cell is read out onto that bit line of each bit line pair which is not connected to the memory cell that is currently to be read out. In this case, a high logic level is stored in the reference cell of one bit line pair and a low logic level is stored in the reference cell of the other bit line pair. Afterward, the two bit lines onto which the content of the reference cells has been read out are short-circuited together. In this way, a reference potential is established on these two bit lines, the reference potential approximately corresponding to the average value of the two potentials previously generated on the bit lines.
In order to generate the reference potential, then, it is important that in each case different potentials are stored beforehand in the two reference cells. For this purpose, the two U.S. patents mentioned above provide special devices which cause the different potentials to be written to the reference cells.
It is accordingly an object of the invention to provide an integrated memory configuration and a method of operating an integrated memory configuration which overcome the above-mentioned disadvantages of the heretofore-known memory devices and methods of operating such memory devices of this general type and with which the generation of two different potentials in reference cells of two bit line pairs is effected utilizing components that are already present.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory configuration, including:
a plurality of word lines;
four reference word lines;
bit lines including two bit line pairs;
memory cells provided at crossover points between each of the word lines with a respective one of the bit lines of each of the two bit line pairs;
reference cells provided at crossover points between each of the four reference word lines and a respective one of the bit lines;
two differential sense amplifiers connected to a respective one of the two bit line pairs;
two first switching elements connecting a respective one of the bit lines of a first one of the two bit line pairs to a respective one of the bit lines of a second one of the two bit line pairs; and
two second switching elements respectively connecting one of the reference cells of one of the two bit line pairs to a given one of the bit lines of another one of the two bit line pairs, the given one of the bit lines of the another one of the two bit line pairs not being connected, via a corresponding one of the two first switching elements, to one of the bit lines assigned to the one of the reference cells of the one of the two bit line pairs.
In other words, the memory according to the invention has word lines, at least four reference word lines and two pairs of bit lines. Furthermore, it has memory cells, which are provided at crossover points of each word line with a respective bit line of each bit line pair. Furthermore, it has reference cells, which are provided at crossover points of each reference word line with one of the bit lines. Two differential sense amplifiers are connected to a respective one of the bit line pairs. The memory has two first switching elements, which respectively connect a bit line of the first pair to a bit line of the second pair, and also two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell.
In this case, the first switching elements serve for short-circuiting the bit lines connected to them, in order to generate a reference potential, required for the evaluation of a differential signal by the sense amplifiers, in the manner described above with reference to U.S. Pat. Nos. 5,572,459 and 5,844,832. The second switching elements serve for writing back suitable potentials to the reference cells again after an evaluation carried out by the sense amplifiers, or after amplification of the differential signal present at the sense amplifiers. The second switching elements make it possible for this writing-back to be carried out through the use of the sense amplifiers that are present anyway.
The invention is therefore preferably suitable for use in integrated memories with reference cells whose content is destroyed during read-out and which therefore has to be re-established after read-out. Memories of this type are DRAMs and FRAMs, for example. The second switching elements make it possible, during this writing-back, to connect both previously read-out reference cells to the same sense amplifier. Since each activated sense amplifier generates mutually complementary potentials at its terminals, this ensures that mutually complementary potentials are written to the two reference cells.
If writing-back of potentials to the reference cells through the use of the sense amplifiers were provided without the second switching elements being present, these potentials would be dependent on the datum of the normal memory cell that had previously been read out by the sense amplifier. Therefore, it would then be possible for the same potential to be written to both reference cells, for which a common short-circuit element in the form of the first switching element is provided. This is not permissible, however, since, as explained previously, different potentials must be written to these two reference cells for the generation of the desired reference potential.
Due to the fact that the sense amplifiers can be used for writing information items to the reference cells on the basis of the presence of the second switching elements, the two different potentials (logic xe2x80x9c1xe2x80x9d and logic xe2x80x9c0xe2x80x9d) are fed to the reference cells in the same way as corresponding data to be written are fed to the normal memory cells. Since the information to be written is supplied by the sense amplifier in both cases, the described generation of the reference potential takes place in a way which is adapted to the operation of writing to the normal memory cells.
According to another feature of the invention, the reference cells have a selection switching element, whose control terminal is connected to the corresponding reference word line and whose first terminal of its controllable path is connected to the corresponding bit line, and, in those two reference cells which are connected via the second switching elements to a bit line of the other pair, the second terminal of the controllable path of their selection switching element is connected to the corresponding second switching element.
According to yet another feature of the invention, the second switching elements have control terminals connected to different control lines in each case.
According to another feature of the invention, the second switching elements have control terminals connected to a common control line.
With the objects of the invention in view there is also provided, a method of operating an integrated memory configuration, the method includes the following steps:
providing an integrated memory configuration having memory cells, reference cells and two bit line pairs connected to respective differential sense amplifiers;
reading out a first one of the reference cells onto a bit line of a first one of the two bit line pairs and reading out a second one of the reference cells onto a bit line of a second one of the two bit line pairs;
short-circuiting the bit line of the first one of the two bit line pairs and the bit line of the second one of the two bit line pairs;
reading out given ones of the memory cells onto respective other bit lines of the two bit line pairs;
amplifying, with the differential sense amplifiers, differential signals established on the two bit line pairs;
decoupling a given reference cell selected from the group consisting of the first one of the reference cells and the second one of the reference cells, after having been read out, from a corresponding one of the differential sense amplifiers connected to a bit line associated with the given reference cell;
connecting the given reference cell, after having been decoupled, to a given bit line of a corresponding other one of the two bit line pairs, the given bit line having previously not been short-circuited with a bit line assigned to the given reference cell; and
simultaneously writing back a differential signal amplified by one of the differential sense amplifiers to one of the given ones of the memory cells having been read out and to the first one and the second one of the reference cells having been read out, and writing back a further differential signal amplified by another one of the differential sense amplifiers to another one of the given ones of the memory cells having been read out.
In other words, in accordance with the operating method according to the invention, in the event of a read access, what takes place is a simultaneous read-out of a respective normal memory cell on each bit line pair. Afterward, one of the second switching elements brings about the situation where the two reference cells previously read out are connected to the same sense amplifier. The differential signal amplified by this sense amplifier is then written back simultaneously to one of the read-out memory cells and to the two read-out reference cells connected to it, and the reference signal amplified by the other sense amplifier is written back to the other read-out memory cell. The writing-back to the memory cells and reference cells advantageously takes place relatively rapidly on account of the simultaneity.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells and reference cells, and a corresponding operating method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.